Tara Vishin
Lead Analog Design Engineer at Cadence Design Systems
- Role
- Lead Analog Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Tara Vishin
High speed Transmitter/driver block design for upcoming DDR-IO standards -Pre-Emphasis and Feed Forward Equalization in High speed memory Transmitters to improve channel performance-Bias generators-Linear amplifiers and buffers- High Speed Receiver for USB2- Comparators- Samplers- Charge Pump based level shifters
Experience
Lead Analog Design Engineer
Sep 2020 — Present · Bangalore Urban, IN
Education
Indian Institute of Science (IISc)
ME ,Microelectronics, Microelectronics
2013 — 2015
Ramaiah Institute Of Technology
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
2008 — 2012
Delhi Public School - R. K. Puram
11th-12th
2006 — 2008
Skills
- Cadence
- Xilinx Ise
- Analog Circuits
- Eldo
- Matlab
- Latex
- Analog Circuit Design
- Verilog
- Vlsi
- Vhdl
- Tcad
- C
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