Tapodhan Reddy

About Tapodhan Reddy

Responsible for physical designs which includes synthesis, floor planning, power-grid and clock tree designs, place and route (PnR), Static Timing Analysis (STA), timing closure, RC-extraction, DFM and DRC clean-upVerify the physical designs through sign-off verification flows, such as functional equivalency verification (FEV), performance verification (PV), Signal Integrity/Noise, layout design rules verification (LV), reliability verification (RV)Automation with TCL, Perl, & Python languagescollaborate with partner domains like Architect, Logic, TFM, test, etc, for design convergence

Experience

1. Mts Silicon Design Engineer

   AMD

   May 2025 — Present · Bengaluru, IN

   VLSI physical design implementation

Education

• BV Raju Institute of Technology (BVRIT)

  Bachelor’s Degree, Electronics and Communications Engineering

  2006 — 2010

• Sree Vidya Peeth, Narketpally, Nalgonda

  Secondary School, Central Board of Secondary Education

  1996 — 2001

• VEDA IIT

  Diploma, VLSI Physical Design

• Gurukul Vidhya Peeth, Ibrahimpatnam, Hyderabad

  High School, High School/Secondary Certificate Programs

  2001 — 2004

• Narayana junior college

  Board of Intermediate, Andhra Pradesh, Mathematics, Physics, & Chemistry

  2004 — 2006

• College Of Engineering, Osmania University

  Master’s Degree, VLSI DESIGN & EMBEDDED SYSTEMS

  2011 — 2013

Skills

• Floorplanning
• Clock Tree Synthesis
• Perl
• Timing Closure
• Synopsys Primetime
• Shell Scripting
• Cadence Encounter
• Tcl
• Static Timing Analysis
• Place & Route
• Eco