Tapas Kumar Ojha
Pre-Si Verification Engineer at Intel Corporation #iamintel
- Role
- Pre-si Verification Engineer at Intel
- Location
- Cuttack, OD, IN
- LinkedIn followers
- 500 followers
About Tapas Kumar Ojha
M.Tech in Microelectronics and VLSI design from NIT Sikkim (pass-out 2018) with 5+ yrs of experience in the front-end verification. currently working as DV engineer in Intel technology with proficient level knowledge in SV, UVM, in addition to the AMBA AHB, Ethernet protocol MAC layer, MOESI cache coherency, Tile-link protocol MIPI(DSI,DPHY) and MIPI-SneekPeak knowledge.
Experience
Pre-si Verification Engineer
Nov 2021 — Present · Bengaluru, IN
Working on verifying one DFD IP. This IP is a gateway for the debug software to analyze the many issues in SOC.This is an amazing IP with lots of features for efficiently tracing the data from SOC using i3c (a two-wire solution).I am verifying the features by creating a test-plan, developing test cases and scoreboard for different features.Note: This is an IP with amazing features, if you want to use it for your SOC, contact INTEL.
Education
Choudwar College,Choudwar
Intermediate in Science, Intermediate in Science
2005 — 2007
National Institute Of Technology Sikkim
Master’s Degree, M.Tech in Microelectronics and VLSI Design
2016 — 2018
Sadhu Sundar Bidyapitha
Matriculation, Matriculation
2000 — 2005
Synergy Institute of Engg. And Tech.,Dhenkanal
Bachelor of Technology (B.Tech.), Electronics and Telecommunication Engineering
2007 — 2011
Skills
- Sdh
- C++
- Operating Systems
- Gsm
- Pdh
- Team Management
- Dwdm
- Nms
- C
- Vhdl
- Linux
- Transmission
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