Tanmay Joshi
Design Verification (DV) Intern @Tata Consultancy Services | M.Tech VLSI Design ’26 @ VIT Vellore | Open to All VLSI Roles
- Role
- Design Verification Intern at Tata Consultancy Services
- Location
- Mumbai, MH, IN
- LinkedIn followers
- 500 followers
About Tanmay Joshi
M.Tech VLSI Design student at VIT Vellore with strong interest in ASIC Design and Verification. Currently working as a Design Verification Intern at Tata Consultancy Services (TCS).Skilled in SystemVerilog, Verilog, UVM, FPGA design, and ASIC Physical Design flows using Synopsys tools. Experienced in RTL design, verification methodologies, and FPGA-based implementations. Also worked on Cadence Virtuoso for Schematic level simulations like DC, AC and Transient analysis of circuits.Actively seeking opportunities in ASIC Design, Verification, Physical Design, and FPGA engineering.
Experience
Design Verification Intern
Feb 2026 — Present
Currently working on UVM Based Verification of AXI Protocol
Education
St. Francis D'Assisi High School
SSC
2007 — 2017
Vellore Institute of Technology
Master of Technology - MTech, VLSI Design
Vidyalankar Institute of Technology, Mumbai
Bachelor of Engineering - BE, Electronics and Telecommunications Engineering
2019 — 2023
Nirmala Memorial Foundation College of Commerce & Science
HSC
2017 — 2019
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