Tani Aguayo

About Tani Aguayo

Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.At AMD, my role as a Memory Firmware Engineer centers around the development of cutting-edge firmware for DDR5 PHY and DRAM Training, ensuring robust, high-frequency link reliability. Our team\'s collaborative efforts have resulted in significant post-silicon enhancements, defining feature specs that push the boundaries of SoC performance. Previously, as a Senior Hardware Engineer at Samsung Semiconductor US, I co-designed hardware and software for a GPS receiver optimized for battery-powered applications. This role honed my skills in power delivery and hardware engineering, where I led the development cycle of performance testing boards and spearheaded power consumption analysis, directly contributing to the evolution of cell phone motherboards and SoC systems.

Experience

1. Asic Design Engineer

   Micron Technology

   Nov 2025 — Present · Folsom, CA, US

   Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development. 10+ years of experienceSoC Arch• Architect to look into Full end2end Data-path• Drive initialization, reset flow and design implications to other blocks• Drive Different Clock domain crossing, distribution and dependency• Drive Power-domains, level-shifting, power-management requirement• Drive DFX requirement - including BSCAN, JTAG

Education

• Universidad Autónoma de Madrid

  Master's Degree, Electrical and Electronics Engineering

  2003 — 2005

• Oregon State University

  Post Doctoral Degree, Electrical and Electronics Engineering

• Universidad Autónoma de Madrid

  Doctor of Philosophy (Ph.D.), Electrical Engineering

  2005 — 2007

• Universidad de Granada

  Bachelor's Degree, Electrical and Electronics Engineering

  2003

Skills

• Monte Carlo Simulation
• Matlab
• Latex
• R&D
• Algorithms
• Root
• Characterization
• Digital Signal Processors
• Analog Circuit Design
• Dsp
• Engineering
• Oop
• Geant4
• Programming
• Physics
• Embedded Systems
• Electronics
• Sensors
• Science
• Linux
• Signal Processing
• Circuit Design
• Testing
• C++
• Research and Development (R&D)
• Vhdl
• Simulations
• Semiconductors
• Fpga
• Device Characterization