Amrani Tarek

Dft Engineer @STMicroelectronics

Scan insertion and verification. • On chip Clock Controller insertion (OCC). • Gate Level Simulation of ATPG patterns. • Fault models: stuck-at, transition, IDDQ. • IPs verification with TESTBOX. • Scan patterns test failures debugging, diagnosis, and re-generation. • Collaboration across ST’s multi-sites/multi-countries activities to support test development