Tamal Sinha
Physical Design Engineer @ Google
- Role
- Senior Physical Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Tamal Sinha
1.Responsible for performing the overall backend flow from RTL to GDSII(Synthesis, floorplan, placement, CTS, Routing) along with STA and clearing all possible violation like DRC LVS IR-Drop etc.2. Worked in both Block and SoC level Designs. Implemented critical designs like Fabrics, DDR, PCIE Subsystem, ARM-Core etc.3. Flow and Methodology development for 14nm, 10nm and 7nm designs.
Experience
Senior Physical Design Engineer
Jan 2025 — Present · Bengaluru, IN
Education
West Bengal University of Technology, Kolkata
B.tech, Electronics & communication
2008 — 2012
Skills
- Asic
- Electronics
- Timing Closure
- Cadence Virtuoso
- Digital Circuit Design
- Primetime
- Soc
- Lvs
- Timing
- Physical Design
- Rtl Design
- Circuit Design
- Automation
- Logic Synthesis
- Static Timing Analysis
- Digital Electronics
- Physical Synthesis
- Linux
- Verilog
- Pspice
- Integrated Circuit Design
- Microprocessors
- Vlsi
- Drc
- Perl
- Eda
- Tcl
- Vlsi Cad
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