Takshashila Chunarkar
EDA Methodoligy Engineer, Lattice Semiconductor||RTL analysis, Sign-off, CDC, RDC,Design Constraints|| Cadence Design Systems|| Mixed Signal Design & Verification|| RTL Design|| Research enthusiast
- Role
- Eda at Lattice Semiconductor
- Location
- Pune District, MH, IN
- LinkedIn followers
- 500 followers
About Takshashila Chunarkar
Front end Analog/Digital-Mixed signal design and Verification professional.Conversant with Verilog, SystemVerilog, Verilog A, Verilog AMS.I am well versed with different EDA tools such as Virtuoso suit, AMS Designer, Spectre, Synopsis\' HSPICE, VCS Mentor graphics\' TSPICE, QuestaSi, Xilinix, Altera etc.Research interests are VLSI interconnects, Analog and Digital design, Modeling, Analysis, Simulation Nanotechnology, Optimization, futuristic device technologies like CNTFETs, GNRFETs, Signaling schemes
Experience
Eda
Jan 2026 — Present · Pune, IN
Education
SRTMU University, Nanded
B.E., Electronics
2001 — 2005
Dhirubhai Ambani University
PhD, VLSI
2017 — 2022
Nehru Junior College of Science,Chandrapur
H.S.C., Science
1999 — 2001
Sinhgad College of Engineering,Vadgaon,Pune
Masters of Engineeting, VLSI and Embedded Systems
2008 — 2013
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