Swapnil Pandey
- Role
- Design Verification Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Swapnil Pandey
I am pursuing my Master\'s in Electrical Engineering at San Jose State University and…
Experience
Design Verification Engineer
May 2022 — Present
Skills
- Cadence Virtuoso
- Programming
- Python
- Hibernate
- Apache Tiles
- Microsoft Office
- Java
- Universal Verification Methodology (Uvm)
- Static Timing Analysis
- Pspice
- Vhdl
- Very-Large-Scale Integration (Vlsi)
- Field-Programmable Gate Arrays (Fpga)
- C++
- Teamwork
- Microsoft Powerpoint
- Computer Architecture
- Matlab
- C
- Verilog
- Java Applets
- Public Speaking
- Struts 2
- Adk
- Jsp
- Synopsis
- Systemverilog
- Application-Specific Integrated Circuits (Asic)
- Spring Mvc
- System on a Chip (Soc)
- Powerpoint
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