Swapnil Vairale
Principal Design Engineer at Cadence Design Systems
- Role
- Principal Design Engineer at Cadence
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Swapnil Vairale
A smart RTL Design VLSI engineer with significant experience in ranging from Design,Validation, Architecture to verification.
Experience
Principal Design Engineer
Nov 2020 — Present · Pune, IN
Education
IIT Kharagpur
Master of Technology (MTech), Microelectronics and V.L.S.I.
2012 — 2014
COEP Technological University
Bachelor of Technology (BTech), Electronics & Telecommunication Engineering
2007 — 2011
Skills
- Simulink
- Engineering
- Shell Scripting
- Electronics
- Vhdl
- Simulations
- Perl
- C
- Programming
- Labview
- Microcontrollers
- Matlab
- Algorithms
- Catia
- Linux
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.