Swapnil Daware
STA Engineer(static timing analysis)
- Role
- Physical Design Timing Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Swapnil Daware
I am actively looking for better opportunity in VLSI / Semiconductor industry with following skills and skills-> Static timing analysis -STA -> Physical Design (RTL to GDSII)-> EM,IR Analysis -> 7nm/10nm/28nm Basic Knowledge->Circuit design and SPICE Simulation ->Cross Talk and Signal Integrity->Simulation, Verification Concepts-> Digital Circuit Design -> Hands on RTL/ASIC designing in Verilog HDL. Languages->Scripting language: Tcl, Python->Basics of C, Object Oriented Programming ->Verilog HDL->System Verilog
Experience
Physical Design Timing Engineer
Jul 2024 — Present · Bengaluru, IN
Education
COEP Technological University
Master's degree, VLSI Design
2018 — 2020
Shri Ramdeobaba College of Engineering and Management
Bachelor of Engineering, Electronics and communication
2011 — 2015
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