Suvendu Saha
Application Engineer Staff at Synopsys | Former Principal product validation engineer at Cadence Design Systems
- Role
- Staff Application Engineer at 新思科技股份有限公司
- Location
- Faridabad, HR, IN
- LinkedIn followers
- 500 followers
About Suvendu Saha
Currently working as an Application engineer where my responsibilities are Qualification of VCS through Onsite testing, Customer engagement and debugging of design failures followed by providing solution/Workarounds till issue gets resolved in Simulator.Previously worked as Principal Product validation Engineer in Cadence Design systems having 9 yrs of experience in Verilog / SystemVerilog and mixed-language where being a first user my job involves writing tests in Systemverilog / UVM to validate features implemented in simulator. Experience in all levels of testing, including Performance, Functional, Integration, System, Regression and User acceptance testing. Works Include - Implementing Unit and Integration tests in systemverilog to consistently deliver high quality features- Coordinate continued performance assurance of software applications and automated performance test scripts- Identified areas of the application to be regression tested- Verification of SystemVerilog features (functional and performance) implemented in Xcelium through automation (using Python) which includes random test generation covering different constructs and scenarios- Responsible for giving trainings on SystemVerilog to new joiners.
Experience
Staff Application Engineer
Feb 2024 — Present · Noida, IN
Education
Al-Falah school of engineering and tech
Bachelor of Technology (B.Tech.), Electronics and Communications Engineering
2005 — 2009
Modern School
Non-Medical
1991 — 2004
CDAC - Noida
PG diploma, VLSI
2011 — 2011
Skills
- Verilog
- Asic
- Tcl
- Vlsi
- C
- Unix
- Linux
- Modelsim
- Systemverilog
- Rtl Coding
- Rtl Design
- Testing
- Soc
- Formal Verification
- Vhdl
- Embedded Systems
- Eda
- Functional Verification
- Debugging
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