Suvarna Yenumula
Aspiring DFT Engineer | VLSI | Scan, ATPG & Test Concepts
- Role
- Dft Trainee at Vlsiguru Training Institute
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Dft Trainee
Nov 2025 — Present · Bengaluru, IN
Currently undergoing professional training in VLSI Design for Testability (DFT) at VLSIGuru• Learning core DFT concepts such as Scan Design, ATPG, Fault Models, and Test Flow• Gaining hands-on exposure to industry-oriented DFT methodologies• Actively improving technical and analytical skills in VLSI testing domain• Passionate about learning and building a career in DFT/VLSI domain
Education
Sri Padmavathi Mahila Visva Vidyalayam, Tirupathi
Btech, Computer Engineering
2020
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