Susmi Das
EUV and Hi Na lithography resist evaluation | Dry Krf/Arf PFAS free resist evaluation | Immersion lithography track engineer | Team lead | Customer engagement | Ex-Intel .
- Role
- Principal Process Engineer at Microchip Technology Inc.
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Susmi Das
Experienced Lithography Process Engineer with 11 years in semiconductor manufacturing, specializing in sustaining and development of 14nm and 10nm front-end FIN layers, immersion track tool ownership and resist evaluation for dry Krf/ dry Arf/ immersion/ EUV/ Hi-NA lithography tools.Demonstrated ownership of immersion track systems and strong attention to detail and consistent delivery of high-quality results. Successfully trained and onboarded new engineers, ensuring rapid integration and operational readiness.Conducted evaluation of novel metal oxide resist on EUV lithography systems with pilot run to monitor daily CD/ defect trend for baseline trending and presented data to upper forum. Led project on litho side and worked in collaboration with thin films/ etch module for dose reduction with minimal impact/ improvement on process window performance and defectivity.Led evaluations of Per- and polyfluoroalkyl substances free (PFAS-free) chemically amplified photoresists for dry KrF/ArF lithography in response to evolving government environmental regulations. Focused on via and grating layer applications, working with multiple vendors to assess performance and patterning quality. Delivered continuous feedback to vendors, driving material improvement. Acted as team lead, providing technical guidance, troubleshooting support, and ensuring tool and process functionality across all stages of resist evaluation.Evaluated ample of small and gallon samples of chemically amplified photoresists on immersion, EUV and Hi-NA lithography tools for contact/hole layers using CD-SEM and Fractilia for pattern fidelity and defect analysis. Worked on contact/ holes evaluation using both binary and embedded phase shift masks (ePSM), selecting mask type based on critical dimension (CD) pitch requirements.
Experience
Principal Process Engineer
Apr 2026 — Present · Gresham, OR, US
Education
University of Mumbai
Bachelors, Engineering
2001 — 2005
University of Houston
Masters, Electrical Engineering
2007 — 2009
University of Houston
Doctor of Philosophy (PhD), Electrical Engineering
2009 — 2014
Skills
- Instrumentation
- Versapro
- Cadence Virtuoso
- Matlab
- Calp
- Optical Lithography
- Xilinx
- Sem
- Autocad
- Silvaco
- Electrical
- Wet Etching
- Etching
- Integrated Circuit Design
- L-Edit
- Fpga
- Vhdl
- Psoc
- Plasma Etch
- Lvvl
- Confocal Microscopy
- Labview
- Comsol
- Verilog
- Pspice
- Afm
- Xps
- Lvdac-Ems
- Mathcad
- Altera Quartus
- Solidworks
- Photolithography
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