Sushmitha Ramesh
Pre-Silicon Verification Engineer | System Verilog | FPGA Functional Verification
- Role
- R & d Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sushmitha Ramesh
Pre-Silicon Verification Engineer with over four years of hands-on experience. I specialize in functional verification.My expertise spans developing comprehensive verification environments utilizing SystemVerilog and designing and executing directed and constrained-random test cases to meticulously validate complex RTL designs.I am proficient in utilizing industry-standard simulation and debugging tools such as Synopsys VCS and Verdi, which enhances my ability to identify and resolve intricate design issues effectively. My strong skills complement this capability in debugging using waveform viewers like DVE and my adeptness in scripting languages, including Perl, Tcl, and Shell, which I employ to automate verification tasks and improve efficiencies in regression management. Familiarity with protocols such as AXI-ST, AXI-Lite, PCIe Gen6, AVST, AVMM, and I2c.
Experience
R & d Staff Engineer
Jun 2025 — Present
Education
Vellore Institute of Technology
Master of Technology - MTech, VLSI
2018 — 2020
Maharaja Institute of Technology
B.E, Electronic and Communications Engineering
2014 — 2018
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