Sushil Kumar
FPGA/ASIC Design Engineer.
- Role
- Developer 1 at Evon Technologies
- Location
- New Delhi, IN
- LinkedIn followers
- 500 followers
About Sushil Kumar
A motivated and enthusiastic FPGA/ASIC Design Engineer having 3+ years of experience. Language : Verilog, VHDL, C, C++. Tools : ISE Navigator 14.7, Xilinx Vivado 2022.1, Cadence Ncsim, Cadence Genus(Legacy Mode), Cadence Jasper Gold Superlint and CDC Verification app, Cadence OrCAD for PCB design, Putty (SSH and Serial Communication), Tera term, WinScp. FPGA boards handson like Nexys Artix 7, Basys 3 and Zynq Ultrascale Mpsoc Zc104, Zcu208 Rfsoc, Embedded Boards Handson : BeagleBone Black Board. Skills: Amba protocols :[APB,AHB,AXI], I2C,SPI, UART, RTL Debugging, SOC RTL Integration, TCL Scripting, CDC and linting, Constraining the design, low power synthesis, Circuit Design, Schematics Capture, Layout design, Gerber file generation.
Experience
Developer 1
Feb 2025 — Present · Dehradun, IN
Education
Maharaja Surajmal Institute Of Technology
B.Tech
2018 — 2021
PinE Training Academy LLP
A+
2021 — 2022
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