Surya B.

About Surya B.

A Silicon Engineer at Google with over four years of experience in physical sign-off, flow development, and methodology optimization. Collaborated with CAD teams and vendors to establish robust environments for execution at both IP and SoC levels. Played a pivotal role in dashboard implementation and audit automation, contributing to enhanced process efficiency. Expertise includes debugging DRC, ERC, LVS checks, timing ECO implementation, and setting up PV sign-off flows for advanced nodes like tsmc n2. Previously served as Senior R&D Engineer IC Design at Broadcom, delivering full-chip integration, top-level routing, and sign-off across multiple advanced nodes. Proficient in addressing bulk DRCs, custom routing for critical nets, and floor planning. Dedicated to advancing GPU methodologies and enabling seamless physical verification processes through collaborative efforts and innovative solutions.

Experience

1. Silicon Engineer

   Google

   Jan 2021 — Present · Bengaluru, IN

   Carried out flow development work for back-end sign-off and implementation in collaboration with CAD team. Collaborated with vendors to set up functioning environment for executions at both IP and SoC level.• Driven 80% dashboard implementation activities and also contributed towards audit automation metrics which is at 70% completion stage.• Debugging and addressing DRC, ERC and PERC, LVS checks and Soft check and Timing ECO\'s implementation for blocks.• Established PV sign-off flow 4lpe Samsung node for smoother block convergence minimizing congestion and hotspot from floorplan to route opt.• Validated the 4lpe deck for signoff rules in collaboration with foundry and tool vendors.• Currently being part of GPU team has been guiding the PD team on the floorplan issues, on placement of Physical IP’s and router related feedbacks.

Education

• GITAM University

  M.Tech, VLSI Design

  2009 — 2011