Surya P

Analog Layout Engineer | Passionate about Analog & Custom Layout | VLSI Enthusiast | Capgemini Engineering

Role
Associate at Capgemini Engineering
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Surya P

Hello! I am Surya, a passionate analog layout engineer with hands-on experience in advanced process nodes (5 nm FinFET), currently working on designing and implementing precision analog blocks. My foundation in memory layout has equipped me with strong fundamentals in floor planning, device placement, routing, and physical verification—skills I now apply and refine in the world of analog custom layout.I specialize in schematic-driven layout (SDL), and work closely with circuit designers to meet stringent performance, matching, and parasitic goals. I’ve developed a sharp eye for layout symmetry, routing discipline, EM/IR-aware design, and tapeout-quality DRC/LVS closure.With a growing passion for deep analog concepts and high-performance custom design, I’m continuously learning and evolving to take on more complex layout challenges.

Experience

  1. Associate

    Capgemini Engineering

    Apr 2024 — Present · Bengaluru, IN

    Analog Layout Engineer -Leading experimental analog layout development in collaboration with Intel - Collaborating closely with circuit designers and senior layout engineers to optimize performance, area, and parasitic targets during floorplanning and final layout implementation-Performing thorough layout verification using Cadence Virtuoso, ensuring DRC, LVS, and ERC clean designs with adherence to foundry rules and project specs-Maintaining documentation of layout processes, reviews, and feedback cycles for traceability

Education

  • New Horizon College of Engineering

    Bachelor's degree, Electronics and communication

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Surya P — Associate at Capgemini Engineering in Bengaluru, KA, IN | Unifers