Surya Reddy
Soc DFT Design Engineer
- Role
- Soc Dft Design Engineer at Intel
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Surya Reddy
M.Tech with 13 years of Experience as a DFT Engineer-Hands on DFT design/implementation/validation/production testing of SCAN, SSN, JTAG, Compression, Tessentmbist, IJTAG, Boundary Scan, BIST etc-Experience in Handling Fabric/Sector DFT for Intel FPGA Designs-Experience in DFT ATPG vector generation/gate level verification/post silicon testing-Experience in MentorGraphics, Tetramax, ET, Logic Vision, NCSIM/VCS, Debussy-Knowledge on Perl/Make-Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models- Knowledge in memory defect models and test algorithms- Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing.
Experience
Soc Dft Design Engineer
Jul 2022 — Present · Penang, MY
Education
GITAM INSTITUTE OF TECHNOLOGY
M.Tech, Digital Systems & Signal Processing
2008 — 2010
Skills
- Timing Closure
- Jtag
- Cadence
- Asic
- Bist
- Static Timing Analysis
- Atpg
- Vlsi
- Simulations
- Physical Design
- Low-Power Design
- Logic Synthesis
- Soc
- Debugging
- Dft
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