Surya Narayana Rangavajhala

About Surya Narayana Rangavajhala

RTL Design Engineer | Digital Logic & SoC Design | VLSI Development University of Hyderabad | 3 Years Experience in FPGA DesignI’m an RTL Design Engineer with 3 years of hands-on experience in FPGA development, RTL coding in Verilog/SystemVerilog, and system-level design. I bring a strong foundation in digital design, backed by an M.Tech in Integrated Circuit Technology from the University of Hyderabad. In addition to my hardware expertise, I have 1 year of experience in Python and C, which has helped me bridge the gap between hardware and software through co-design and embedded systems development.My work spans across FPGA-based SDR systems, DSP block design, and high-speed data transfer using AXI DMA. I\'ve contributed to complex projects including S-band SDR development and DSP filter design, with a focus on achieving timing closure, optimizing resource utilization, and implementing reliable CDC mechanisms. I have experience with Xilinx tools (Vivado, Vitis), ILA debugging, and platforms like ZC706 and ZC702.I’m also proficient in using test and measurement tools like oscilloscopes, logic analyzers, and spectrum analyzers, and I’m comfortable with version control using Git. Whether it’s developing custom IP blocks, integrating communication protocols (AXIS, JESD, SPI), or writing embedded C for DMA configuration, I’m driven by building robust, real-time hardware systems.

Experience

1. Design Engineer 2

   Blaize

   Feb 2026 — Present · Hyderabad, IN

Education

• University of Hyderabad

  Master's of Technology, Integrated Circuit Technology

• CVR College of Engineering, Hyderabad

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2015 — 2019