Surya Ramasamy
Pre-Si Valid/Verif Engineer | SystemVerilog | UVM |
- Role
- Pre-si Valid Verif Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Pre-si Valid Verif Engineer
Dec 2020 — Present · Bengaluru, IN
Experienced Pre-Si Validation Engineer proficient in SystemVerilog, UVM, and functional verification. Skilled in developing scalable verification plans, test benches, and environments to ensure designs meet specifications. Passionate about uncovering bugs and ensuring high-quality microarchitecture.
Education
K.S.Rangasamy College of Technology
Bachelor of Engineering - BE
2012 — 2016
SRK Matriculation higher secondary School
HSC
2010 — 2012
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