Suryaprabakaran M

About Suryaprabakaran M

Major / Background“I have completed my B.E. in Electronics and Communication Engineering, with hands-on experience in VLSI Physical Design. I have trained and worked on ASIC flow, from floorplanning to design sign-off.”Duties / ResponsibilitiesWorked on floorplanning, placement, clock tree synthesis (CTS), and routing at block level.Performed Static Timing Analysis (STA) across PVT corners and resolved setup/hold violations.Conducted power integrity checks (IR drop ) and optimized floorplan for better reliability.Familiar with industry Synopsys Tools (PrimeTime,ICC2 )Highlights / AchievementsSuccessfully reduced timing violations by optimizing critical paths and skew.Designed efficient power grids ensuring <5% IR drop.Closed designs at 40nm node with improved placement density and reduced congestion.Strong foundation in ASIC flow, library analysis (.lib.lef.gds), and sign-off checks

Experience

1. Application Specific Integrated Circuit Engineer

   Rv Skills Design Centre

   Jan 2025 — Present · Bengaluru, IN

   I have completed my VLSI course at RV SKILLS, where I contributed to a low-power design with 9 power domains, implementing multi-voltage techniques (1.18V high, 1.1V low) on a block with ~4K standard cells and 39 macros, targeting a 1GHz clock frequency. I gained hands-on experience in the ASIC Physical Design flow, covering floorplanning, placement, CTS, routing, and STA across multiple PVT corners. During this, I resolved setup/hold violations, optimized critical paths, and minimized clock skew for robust timing closure. I successfully closed designs at the 40nm node, improving placement density, reducing congestion, and enhancing reliability. I also performed power integrity analysis (IR drop <5%, EM checks), designed efficient power grids, and worked on physical verification (DRC, LVS, ANT checks) for sign-off readiness. Additionally, I built strong exposure to library analysis (.lib.lef.gds) and industry-standard tools like Synopsys ICC2 and PrimeTime. AchievementsContributed to a low-power multi-voltage design with 9 power domains.Successfully reduced timing violations by optimizing critical paths and minimizing skew.Achieved robust timing closure at 40nm node with improved placement density and reduced congestion.Designed efficient power grids ensuring <5% IR drop and robust EM reliability.Strengthened foundation in ASIC Physical Design flow, sign-off checks, and physical verification.

Education

• Ramakrishna Mission Vidyalaya

  SSLC

• Ramakrishna Mission Vidyalaya

  HSC, Mathematical Biology

• SNS College of Engineering

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

  2021 — 2025