Suruchi Patel

About Suruchi Patel

Senior Design Verification Engineer with 9+ years of experience.I have experience in IP and Sub-System Digital verification.• Deep Knowledge of HDL languages like Verilog, VHDL, HVL language like System Verilog language & Verification Methodology UVM.• Good Understanding on e language and eRM.• Hands on Experience with constrained random verification environments.• Hands on Experience with Assertions based Verification. • Hands on functional coverage modelling.• Good understanding of bus protocols like AMBA protocols, I2C and DMABasic understanding on NVMe and UFS related IP storage device Verification. • Experience in simulations in Synopsys - Verdi, VCS, DVE, Questasim, Riviera-PRO, Cadence-incisive Vmanager, Specman Elite, Xilinx ISE, Tanner Tool. • Good understanding of Block level Test bench Architecture and Verification flow at Block level.• Good Knowledge in both functional and code Coverage Closer.• Hands on Integrating test bench with existing top level TB.• Hands on sequences and test cases development.• Good debugging skills.• Good Documentation skills.• Have good communication skills, interpersonal relations, analytical skills, hardworking and result oriented as an individual and in a team. • Willing to learn new skills and ability to learn fast.Specialities : UVM, System Verilog, Verilog, Synopsys VCS, Verdi, Coverage, IP Level Verification and Sub-system Level Verification.

Experience

1. Senior Staff Engineer

   Marvell Technology

   Dec 2025 — Present

Skills

• Microsoft Excel
• Powerpoint
• Digtal Design
• Very-Large-Scale Integration (Vlsi)
• Fpga
• Asic
• Research
• Systemverilog
• C++
• System Verilog
• Verilog
• Field-Programmable Gate Arrays (Fpga)
• C
• Tanner Tool
• Microsoft Office
• Vlsi
• Xilinx Ise
• Cmos
• Rtl Coding
• Application-Specific Integrated Circuits (Asic)
• Microsoft Word
• Rivera-Pro
• Vlsi Design
• Universal Verification Methodology (Uvm)
• Uvm
• Questa Verification Platform