Suriyanarayanan Ramesh
Solutions Engineering @ ARM | Ex-Qualcomm
- Role
- Staff Engineer - Clocks and Timing Signoff Methodology at Arm
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Suriyanarayanan Ramesh
Courses : • VLSI Design lab under Prof. Gerald Sobelman • VLSI Design I under Prof. Chris Kim • VLSI Design Automation under Prof. Kia Bazargan • Data Structures and Algorithms under Prof. Nathan Taylor • Microelectronic Fabrication under Prof. Stephen Campbell. Skills- Worked on 7nm, 28nm and 45nm technology nodes -Programming Languages: C/C++, Python, Verilog, System Verilog, Cadence SKILL-Tools: Cadence Innovus, HSPICE Circuit Simulator, MATLAB, Virtuoso, Cosmoscope, VCS, Mentor Graphics Calibre (DRC, LVS, PEX). Other: FINFETS, 7nm, Netlist to GDSII, Physical Verification, Digital Logic Design, ASIC Design Flow, Operating Systems – Windows, Unix.
Experience
Staff Engineer - Clocks and Timing Signoff Methodology
Oct 2025 — Present
Education
Amrita Vishwa Vidyapeetham, Coimbatore
Bachelor of Technology, Electronics and Communications Engineering
2014 — 2018
University of Minnesota - Twin Cities
Master of Science - MS, Electrical Engineering
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