Suresh Vemula
Asic Engineer @ Meta | Hardware Design and Verification
- Role
- Asic Engineer at Meta
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Suresh Vemula
As a Senior Principal Engineer, I lead the verification/emulation of complex ASIC/SOC…
Experience
Asic Engineer
May 2025 — Present · Sunnyvale, CA, US
Skills
- Functional Verification
- Open Verification Methodology
- Rtl Design
- Asic
- Very-Large-Scale Integration (Vlsi)
- Systemverilog
- Usb
- System on a Chip (Soc)
- Application-Specific Integrated Circuits (Asic)
- C
- Vlsi
- Vhdl
- Simulations
- Soc
- Universal Verification Methodology (Uvm)
- Debugging
- Perl
- Verilog
- I2c
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.