Suresh Saini

About Suresh Saini

1.~13 years of experience on 2nm, 3nm, 5nm, 7nm, 28nm, 40nm/45nm, 65nm, 90nm, C14(140nm), 180nm Technology for various fab like TI, TSMC, UMC, NXP, Renesas, GF, etc.2. worked on Analog, RF layout and SERDES -> Work involved designing RF modules layout (Rx, Tx, BT, LNA, Mixer, Frequency Synthesizers ) from scratch, design modification, placement & routing to meet the critical constraints like matching & parasitic->Analog modules like analog filters, LDO, line drivers, comparators, reference systems, switching converters, high-frequency building blocks, etc-> verification of layout (LVS, DRC, LPE). worked on IO layout as well-> Work involved designing I/O buffers (Analog, Digital, Signal) for automotive purpose, placement in given constraints, design & verification report documentation-> modules like Input buffer, output buffer, bi-directional buffer, pull-up & pull down, Corner Cells, Filler Cells, Monitor Cells-> ESD layout design-> short verification (LVS, DRC), Full verification (Antenna, Density, EM, Abutment, Latch-up)4. experience on DFM issues, Antenna Effect, EM, ESD, Latch up. Tools Experience Summary - Layout Tools: Virtuoso Layout Editor L/XL/GXL/EXL, Mentor Graphics PysixVerification Tools: Assura (DRC/LVS), Calibre (DRC/LVS), Lavis, PVS (DRC/LVS), ICV(LVS), XOR, PowerPlot, ANT, SVSExtraction Tools : Calibre PEX, star RC, QRC, QRCFSEM/IR: Voltus/Voltus Fi

Experience

1. Senior Staff Engineer

   Marvell Technology

   May 2021 — Present

Education

• B L Ruia (M) High School, Mumbai

  SSC

• Rajasthan Technical University, Kota

  B.TECH, ECE

  2006 — 2010

• Thakur College of Science & Commerce

  FYJC & SYJC, science

  2004 — 2006

Skills

• Standard Cell Layout
• QA (Post Verification) of Layout
• Verilog
• Lvs
• Mixed Signal
• Soc
• Coustom Analog Layout
• Asic
• Verification (Short & Full) of Layout
• Vlsi
• Tcl
• Analog
• Rf
• 40nm
• Static Timing Analysis
• I/O Layout
• Cadence Virtuoso
• Drc
• Rf Layout