Surendra Maddula

About Surendra Maddula

I’m a Senior Product Development Engineer with 8+ years of experience taking complex SoCs from first silicon bring-up to high-volume manufacturing. My core strength lies in developing and optimizing ATE test programs, burn-in content, and scan/MBIST diagnostics that improve yield, reliability, and test efficiency.I’ve led end-to-end validation for multiple SoC families at Intel, collaborating with DFT, design, and manufacturing teams to reduce production escapes by 10–15% and improve yield margins through data-driven debug. My experience spans Intel’s proprietary ATE platforms (CMT, HDMT, SH2, HDBI) along with DFT tools such as Synopsys DFT Compiler, Tetramax, and VCS.I leverage Python and JMP to automate pattern validation, log analysis, and yield correlation — enabling faster diagnosis, improved data visualization, and significant reduction in debug turnaround time.I’m currently seeking Senior to Staff-level opportunities in Product/Test Development, ATE Engineering, or Post-Silicon Validation, where I can apply my hands-on test experience, debug depth, and cross-functional leadership to accelerate bring-up and improve quality in advanced silicon programs.

Experience

1. Product Development Engineer

   Intel

   Nov 2017 — Present

   Developed and optimized Burn-In Test Programs for Intel client and server products, enabling successful HVM ramp and qualification readiness with strong emphasis on DFT strategies and product reliability.Partnered with DFX, Reset, Power, and design teams to establish Burn-In Biasing configurations, ensuring successful hardware initialization and power-on during stress testing.Owned the end-to-end development and validation of SCAN and ARRAY Burn-In modules, delivering high test coverage and robust performance across multiple silicon platforms.Executed detailed post-silicon validation and failure analysis on K-lot WTL and qualification data, identifying root causes and implementing fast-turnaround corrective actions.Validated modules across Intel’s ATE platforms (CMT, HDMT, SH2, HBI), ensuring test accuracy, stability, and alignment with yield and quality goals.Released production-ready test programs to global factories, ensuring seamless deployment, issue resolution, and cross-functional alignment with manufacturing teams.Drove continuous improvements in test efficiency, contributing to PHI goal achievement and reducing test cycle times through iterative optimization.

Education

• Portland State University

  Master's degree, Specialization in Digital IC Design, verification and validation

  2015

• CDAC

  PG DIPLOMA, EMBEDDED SYSTEMS

  2011 — 2012

Skills

• C
• C++ Language
• Linux System Programming
• Device Drivers
• Set Top Box
• Data Structures
• Software Development
• Embedded Systems
• Digital Circuit Design
• Asic
• Verilog
• Vhdl
• C++
• Linux
• Matlab
• Semiconductors
• Debugging
• Embedded C
• Agile Methodologies
• Object-Oriented Programming (Oop)
• Perl
• Core Java
• Linux Kernel
• Python
• Shell Scripting
• System Verilog
• Can Bus
• Iso 26262
• Canoe