Suraj Sindia

About Suraj Sindia

I like to build hardware that works flawlessly—and I make sure it stays that way in the hands of millions.I’m a senior quality, validation, and reliability leader with a Ph.D. in Electrical & Computer Engineering and a proven record driving silicon-level excellence across wireless, analog, and mixed-signal domains. At Intel, I’ve qualified next-gen wireless platforms using statistical modeling, calibration frameworks, and governance systems that scaled across product lines—while securing multiple patents in the process. From early-stage design quality to post-silicon issue closure, I’ve led high-impact initiatives that reduced DPM, improved yield, and delivered high-confidence ramps.But tools and processes are only part of the story. My real strength lies in navigating the messy middle: collaborating across hardware, firmware, manufacturing, and reliability teams—often with competing goals—and still landing risk-mitigating solutions that hold up in the field.I thrive in cross-functional and ambiguous environments, collaborating seamlessly with stakeholders with conflicting priorities.What I Bring to the Table 15+ products (with numerous SKUs) seen through Execution commit to HVM ramp (and improved) Pre/post-silicon validation across analog, digital, RF IP- and SoC-level HVM quality strategy (bring on the heatmaps and shmoo plots!) Expertise in chip reliability, yield, quality modeling and design-for-test TPM & cross-functional leadership across AI & silicon orgs 25+ Patents issued, which were part of shipping products or in wireless standards Fluent in Python, Docker, JMP, SAS, MATLAB, RTLLet\'s connect if you’re building the next generation of hardware and need a senior technical voice in Validation, Quality, or Reliability who sees the whole board—from spec to shipped silicon. I love working on teams at companies where engineering excellence is the culture, not just the tagline.

Experience

1. Engineering Manager

   Intel

   May 2020 — Present

   Manage a small team and technology for modeling Intel\'s Silicon and packaging quality across Client, Server, Chipset products.

Education

• Sri Ramakrishna Vidyashala

  High School

  1998 — 2001

• Seshadripuram College, Bangalore

  Pre-University, Science

  2001 — 2003

• Auburn University

  PhD, Electrical and Computer Engg

  2010 — 2013

• Indian Institute of Science (IISc)

  M.Tech, Electronic Circuit and Systems Design

  2007 — 2009

• RV College Of Engineering

  BE, Electronics and Communication

  2003 — 2007