Suraj Vijay Shetty
CPU DV Intern @Tenstorrent || Ex-Samsung Semiconductor
- Role
- Cpu Dv Riscv Cores at Tenstorrent
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
About Suraj Vijay Shetty
Design Verification Engineer with 4+ years of experience in SystemVerilog/UVM-based RTL…
Experience
Cpu Dv Riscv Cores
Jun 2025 — Present · US
Contributed to ISA verification of RISC-V cores by running compliance suites and debugging failures• Developed assembly-level tests and UVM-based testbench sequences to verify RISC-V ISA compliance and core microarchitectural features.• Developed and enhanced UVM testbench components and refactored existing modules to improve testbench scalability and maintainability.
Education
University of Mumbai
Bachelor of Engineering - BE, Electronics and telecommunication
2016 — 2020
Portland State University
Master of Science (M.S) , Electrical and computer Engineering
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