Suraj Nigave Mtech Iisc Bangalore

About Suraj Nigave Mtech Iisc Bangalore

With 3+ years of experience in IP design verification at Qualcomm, I specialize in UVM-SV based testbench verification environments and coverage-driven methodologies to ensure robust and reusable testbench designs. I hold an M.Tech in Electronic Systems Design from IISc Bangalore, which has strengthened my technical foundation and problem-solving approach across complex verification projects.My expertise spans AXI, APB, and I²C protocols, with hands-on proficiency in tools such as Verdi, QuestaSim, and VCS. Alongside technical delivery, I have mentored engineers at C-DAC Innovation Park, driving both capability building and project success.

Experience

1. Design Verification Engineer

   Broadcom

   Sep 2025 — Present · Bengaluru, IN

   I currently work on verification of high-performance MAC Accumulator hardware used in AI training accelerators. My role focuses on building scalable verification infrastructure and ensuring correctness of mixed-precision compute operations across multiple data formats.I design and develop UVM-SystemVerilog based verification environments at both block level and chip level to validate multiply-accumulate pipelines and memory interactions. The compute engine includes 64 MAC units performing large scale dot-product operations for AI workloads.My work involves validating accumulation modes, memory transactions, and compute correctness across multiple precision formats defined by the OCP Microscaling (MX) specification such as MX-FP4, MX-FP6, MX-FP8, INT8 and BF16 with E8M0 scaling. These formats enable efficient AI training by using reduced precision arithmetic while maintaining model accuracy. OCP_Microscaling Formats (MX) v1.0 Spec_Final.pdf NoneI build detailed reference models to verify arithmetic precision, rounding behavior, saturation handling, and scaling logic. I also create reusable UVM sequences to stress compute and memory pipelines and uncover corner cases such as normal/subnormal transitions, mixed precision interactions, overflow and underflow scenarios.Working closely with architecture and design teams, I debug complex numerical mismatches and ensure the implementation fully aligns with the compute specification. My focus is to achieve strong coverage, scalable regressions, and early detection of corner-case issues before silicon.

Education

• Indian Institute of Science (IISc)

  Master in Technology, Electrical, Electronics and Communications Engineering

• Savitribai Phule Pune University

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering