Suraj Patil

About Suraj Patil

Highly motivated and results-oriented ASIC Digital Design Verification Engineer with 4.5 years of experience in pre-silicon verification, specializing in complex protocols and IP development. Proven expertise in creating comprehensive UVM test environments, developing constraint-random test generation (CRG), assertions, and functional coverage for high-speed interfaces like SerDes (Rx) and USB PD Type-C.Adept at SoC RTL and Gate Level Simulation (GLS), managing regressions, and significantly improving functional and code coverage. Possesses hands-on experience in verifying key digital IPs including UART, LIN, Timer, CRC, and PWM. Familiar with AMBA-APB and AMBA-AHB protocols. Strong collaborator with IP design teams, verification leads, and architects to ensure robust feature coverage and delivery of high-quality designs. Experienced in mentoring new engineers through hands-on training and design exercises. Strong engineering professional with a Master of Technology - MTech focused in VLSI and Electronic Systems from IIT Bomaby and BTech focused in Electronics Engineering from Walchand college of engineering, Sangli.

Experience

1. Lead Design Engineer

   Cadence

   Jan 2026 — Present · Pune, IN

Education

• Indian Institute of Technology, Bombay

  Master of Technology - MTech, Electronic systems

• Walchand College of Engineering(A Govt. Aided Autonomous Institute),SANGLI-M.S

  Bachelor of Technology - BTech, Electronics Engineering