Surajit Bera
Mask Design Engineer at Nvidia
- Role
- Senior Mask Design Engineer at NVIDIA
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Surajit Bera
Good knowledge of Device physics, Fabrication steps of CMOS, FINFET, Memory Layout, physical Verification (DRC, LVS), Reliability checks, ERC, DFM, EMIR, scripting automation.Worked on Layout Designing of memory compiler.Working on Layout Designing of Custom Memories & Security IPs.Tech nodes : 2nm, 3nm, 4nm, 5nm, 10nm, 12nm and 16nm.Scripting Languages known-*BASH scripting *TCL/Tk scripting
Experience
Senior Mask Design Engineer
Apr 2024 — Present · Bangalore Urban, IN
Education
PinE Training Academy
ASIC Design and Full Custom Layout
2018 — 2019
INDERAPRASTHA ENGINEERING COLLEGE, GHAZIABAD
Bachelor of Technology, Electronics and Communications Engineering
2015 — 2019
Motivational Pathway
Bachelor of Technology - BTech, Electronics and Communications Engineering
2015 — 2019
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