Suraj Panwar
- Role
- Engineer Timing Signoff Dft at TSMC
- Location
- Delhi, IN
- LinkedIn followers
- 500 followers
About Suraj Panwar
VLSI professional with experience in physical design and chip-level timing signoff for…
Experience
Engineer Timing Signoff Dft
Sep 2019 — Present
Timing Signoff for advanced nodes (N4P - N12) for HPC applications.\\\\n- Timing closure signoff margin computation for 3DIC based designs.\\\\n- DFT/ Synthesis owner for tapeout projects.\\\\n- Methodology bringup for signoff (MiS, VT-skew, B2T constraint, 3DIC die matching, etc).\\\\n- 2.5 D and 3D Interconnect design and Signoff margin calculation for timing closure.\\\\n- Spice to PT/ Tempus correlation for enabling various features.\\\\n- Channel simulation (Eye diagram analysis, 3D/ 2.5D channel optimization).\\\\n- EM and IR analysis (For enabling DvD annotation in signoff).\\\\n \\\\n\\\\n \\\\n \\\\n\\\\n \\\\n
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