Suraj N Shinde
Lead Engineer Silicon Design Verification | SoC IP Design Verification Engineer | Research Scholar
- Role
- Lead Engineer Design Verification at HCLTech
- Location
- Kolhapur, MH, IN
- LinkedIn followers
- 500 followers
About Suraj N Shinde
I am working as a Lead Engineer for SoC Design Verification having experience particularly in IP Verification using UVM and System Verilog. Hands on experience on Cadence and Synopsys industry tools. Moreover have basic knowledge of AMS verification and Product Management. With respect to education, I have registered to PhD and completed Masters degree in VLSI Design and Embedded System and Bachelors degree in Electronics and Communication. I am good in hardware descriptive languages like VHDL/ Verilog and hardware verification languages like System Verilog and UVM. I am actively looking for a suitable job in VLSI frontend domain.
Experience
Lead Engineer Design Verification
Oct 2025 — Present
Education
Visvesvaraya Technological University
Doctor of Philosophy - PhD, VLSI
Dayananda Sagar College of Engineering, BANGALORE
Master of Technology - MTech, VLSI Design and Embedded System
Gogte Institute of Technology, Belgaum
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
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