Supraja Conjeti

SoC Design Engineer at Intel Corporation

Role
Soc Design Engineer at Intel
Location
College Station, TX, US
LinkedIn followers
500 followers

About Supraja Conjeti

I am an Electrical and Computer Engineering Graduate Student with a Versatile skill set specializing in Digital VLSI and Computer Architecture at Texas A&M University, College Station. As a Passionate Learner & Hard working individual I always look up to \"Making Things Happen\". Another aspect I always hold-on to is \"Working with Quality\" because anything otherwise doesn\'t make sense. I truly believe that working in silos is efficient but working with a great team results in true Synergy! Driven by self-motivation & the need to deliver beyond my roles & responsibilities, I always look forward to contribute to the wholesomeness in terms of Organisation & Self!Contact Email: s•••••••@tamu.edu Skills • Hardware Languages: Verilog, System Verilog, SystemC • Scripting Languages: Perl, Python, Shell, TCL/TK• Methodology: Universal Verification Methodology (UVM), Register Abstraction Layer (RAL)• Software Languages: C, C++ • Bus Protocols : AMBA AXI 3.0, 4.0, AMBA APB, AMBA AHB, UART • VLSI CAD Tools: Synopsys VCS, VISTA, Xilinx ISE, Cadence Virtuoso, Cadence SOC Encounter, Synopsys Design Vision, Prime Time, PSpice, Cadence Incisive, ModelSim, Cadence Spectre• Operating Systems : Linux, Unix, Mac, Windows Interests • IC Verification and Validation • Computer Architecture Design• RTL Design, ASIC /SOC Design

Experience

  1. Soc Design Engineer

    Intel

    Oct 2018 — Present · Austin, TX, US

    Working on Pre- Silicon Verification of Xeon Processors (SoC for Servers)

Education

  • Texas A&M University

    Masters of Engineering, Electrical and Computer Engineering

    2016 — 2018

  • GITAM Deemed University

    Bachelor of Technology (BTech), Electrical and Electronics Engineering

    2012 — 2016

Skills

  • Engineering
  • C
  • C++
  • Microsoft Office
  • Microsoft Excel
  • Programming
  • Matlab
  • Verilog
  • System Verilog
  • Xilinx
  • Universal Verification Methodology (Uvm)
  • Uvm
  • System C
  • Python
  • Cadence Virtuoso
  • Cadence Spectre
  • Soc Encounter
  • Ncsim
  • Synopsys Primetime
  • Vista
  • Psim
  • Assembly Language Programming (Mips)
  • Pspice
  • Data Analysis
  • Project Management

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Supraja Conjeti — Soc Design Engineer at Intel in College Station, TX, US | Unifers