Sai Sunil Chettipalli

About Sai Sunil Chettipalli

EDA Tools Explored:Cadence SOC Encounter, Innovus, Synopsys ICC2 : Floor plan, Placement, Clock Tree Synthesis, RoutingSynopsys Design Compiler Topo : Logic Synthesis HDLs: Verilog and VHDL.CMOS Fundamentals, Digital Design, Synthesis.Physical Design: Floor-Plan, Power Planning, Placement and Routing, Static Timing Analysis, Clock Tree Synthesis, Cross talk Analysis, IR Drop Analysis and Physical Verification

Experience

1. Member of Technical Staff Engineer

   AMD

   Jan 2024 — Present · Hyderabad, IN

Education

• Jawaharlal Nehru Technological University

  Bachelor of Technology (BTech), Electronics and Communications Engineering

  2009 — 2013

• Narayana Junior College, Visakhapatnam

  HSE, Mathematics, Physics and Chemistry

  2007 — 2009

Skills

• Routing
• Cmos
• Physical Verification
• Vlsi
• Prime Time and Prime Time -Si
• Integrated Circuit Design
• Verilog
• Eda
• Static Timing Analysis
• Synopsys Tools
• Digital Design
• Soc
• Asic
• Semiconductors
• System on a Chip (Soc)
• Cadence Encounter
• Signal Integrity
• Vhdl
• Physical Design
• Soc Encounter
• Logic Synthesis
• Electronics
• Clock Tree Synthesis
• Linux