Sunil Pandey

About Sunil Pandey

Broadly working in the analog circuit design in semiconductor industry. Skilled in Cadence Virtuoso, Agilent-ADS, Primetime, Genesys, IC Compiler, SPICE, NI Multisim, LaTeX, Application-Specific Integrated Circuits (ASIC), and TCL. Strong engineering professional graduated from Indian Institute of Information Technology, Design and Manufacturing Jabalpur, M. P, India.

Experience

1. Analog Design

   Samsung Electronics

   Aug 2022 — Present · Bengaluru, IN

   Analog IP Design.

Education

• Indian Institute of Information Technology, Design and Manufacturing, Jabalpur

  Doctor of Philosophy - PhD

  2018

• INSTITUTE OF ENGG. & RURAL TECHNOLOGY,ALLAHABAD

  Bachelor of Technology (B.Tech.), Electronics Engineering

  2006 — 2010

• Jaypee University of Information Technology

  Master of Technology (M.Tech.), Microelectronics Systems

  2010 — 2012

Skills

• Very-Large-Scale Integration (Vlsi)
• System on a Chip (Soc)
• Rtl Design
• Agilent Ads
• Design Compiler
• Languages: Verilog, Basic C, Tcl, Basic Scripting, Matlab, Latex Eda Tools: Mentor Graphics Questasim, Synopsys Design Compiler, Hspice, Tanner, Ledit, Pspice, Cadence Virtuoso and Spectre, Advanced Design System (Ads), Orcad, Ni-Multisim.
• Tcl
• Application-Specific Integrated Circuits (Asic)
• Orcad
• Field-Programmable Gate Arrays (Fpga)
• Analog Circuits
• Latex
• Microsoft Office
• Cadence Virtuoso
• Digital Designs
• Linux
• Modelsim
• Ni Multisim
• Semiconductors
• Electronics
• Matlab
• Synopsys Tools
• Questasim
• C
• Mentor Graphics
• Hspice
• Ledit
• Vhdl
• Simulations
• Cadence Spectre
• Perl
• Verilog
• Pspice
• Embedded Systems