Sunil Pandey

About Sunil Pandey

Hands-on experience working on rtl design with Verilog and VHDL. verification of rtl Design using system Verilog and verilog and vhdl testbench and UVM.Reliable and efficient coding in Vhdl and Verilog with simulation and synthesis on Xilinx ISE and Microsemi Libro.Proficiency of debugging and testing on FPGA virtex6,Sparten6, vertex5, proasic3 and IGLOO2 with Chipscope analyzer, oscilloscope.Configuration and testing of ADC4249, DAC and clock synthesizer.Work on matlab simulink and system generator for modulation and filters.

Experience

1. Senior Design and Verification Engineer

   Collins Aerospace

   Nov 2019 — Present · IN

Education

• College of Technology and Engineering Udaipur.

  Bachelor of Engineering (BE), Electronics and Communications Engineering

  2008 — 2012

• Maa bharati senior secondary school, kota

  12th, Mathematics, physics, chemistry

  2006 — 2007

• Govt Senior Secondary School Bhusawer

  9th to 11th, Mathematics, physics, chemistry

  2003 — 2006

Skills

• Fpga
• Chipscope Pro
• Matlab Simulink
• Fpga Debug
• Linux
• Ise Synthesis
• Vhdl
• System Verilog
• Rtl Design
• Microblaze
• Verilog
• Xilinx Ise
• C
• Oscilloscope
• Isim Simulation
• Matlab System Generator
• Adcs