Sunil M K

About Sunil M K

Dynamic and career oriented engineering professional looking for a Physical Design Engineer position to utilize and enhance my skills towards my professional growth. Currently working as GPU Physical Design Engineer at Intel Technology India Pvt. Ltd.Core Competency:Worked on multiple projects as a block owner owning multiple multi-million gate critical blocks in the latest nanometer node in Graphics/Image processing chips.Core ability in backend design: successfully converged multiple IP blocks starting from floorplan to final tape-in and developed strategies to meet constraints correlated with engineering specifications.PNR, IR drop analysis, STA, IR/RV and ECO.Comprehensive knowledge of Physical Verification i.e. DRC, LVS.Knowledge of Digital Design, RTL Coding, Functional Verification and Verilog coding.Fusion compiler, ICC, ICC2, Primetime and Design compilerWorking Knowledge of Linux and scripting languages.

Experience

1. Gpu Physical Design Engineer

   Intel

   Oct 2016 — Present · Bengaluru, IN

   Working on multiple blocks of graphics multimedia chip across projects in the latest technology node.As partition execution owner worked on multi-million gate critical partitions from netlist to GDSII and developed strategies to ensure design met timing constraints correlated with engineering specifications. Performed automated Synthesis, timing driven Placement, Clock tree synthesis [CTS], Routing, Post-route fixing.Convergence of the design involved timing, layout DRC’s and quality convergence. Timing execution owner of a section, comprising multiple partitions, analyzing inter partition timing and suggesting fixes for the same.Performed Engineering Change Orders (ECOs), setup/hold conflict timing paths fixes, quality fixes.Worked on Synopsys DC-topo, ICC, Lynx and Primetime.Wrote Perl/Tcl scripts for common tasks to improve work efficiency

Education

• Manipal Centre for Information Science

  Master of Science (M.S.)

  2011 — 2013

• Sir M. Visvesvaraya Institute of Technology, Bangalore

  Bachelor of Engineering (B.E.)

  2006 — 2010

Skills

• Asic
• Rtl Coding
• C
• Microsoft Office
• Vlsi
• Vhdl
• C++
• Very-Large-Scale Integration (Vlsi)
• Front-End Coding
• Verilog
• Functional Verification
• Oop
• Systemc
• Perl
• Icc
• Static Timing Analysis
• Digital Electronics
• Physical Design
• Synopsys Primetime
• Uvm
• Tcl
• Data Structures
• Xilinx
• Systemverilog
• Shell Scripting
• Front-End Design
• Linux
• Modelsim
• System Verilog