Sunil
Lead Engineer at Wipro Technologies
- Role
- Lead Engineer at Wipro
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sunil
Experience in developing Test benches in System Verilog using UVM.Experience in using industry standard EDA tools for the front-end design and Verification.Languages: HDL: Verilog.HVL: System Verilog.Methodology: UVM.Scripting Languages: basics of perl.Basics knowledge on SV Assertions.Simulators:Rivera Pro - 2015, Cadence, Mentor Graphics – Questasim, VCS, DVE.Knowledge: ASIC/FPGA Design Flow, RTL Coding, FSM based design, Code Coverage, Functional Coverage, Developing complex TB using UVM.Protocols Knowledge: AMBA APB v3.0, AHB lite,AXI, 10G Ethernet, DDR4.Good debugging skills.
Experience
Lead Engineer
May 2023 — Present · Bengaluru, IN
Education
Dr.Sri.Sri.Sri Shivakumara Mahaswamy College of Engineering
Bachelor of Engineering, Electronics and Communication Engineering
2010 — 2013
RN SHETTY POLYTECHNIC BELGAUM Board Of Technical Education
Diploma, Electrical, Electronic and Communications Engineering Technology/Technician
2007 — 2010
Skills
- System Verilog
- Rtl Coding
- Eda
- Universal Verification Methodology (Uvm)
- Code Coverage
- Amba
- Application-Specific Integrated Circuits (Asic)
- Functional Verification
- Verilog
- Very-Large-Scale Integration (Vlsi)
- Systemverilog
- Amba Ahb
- Modelsim
- Cadence
- Basics of Python
- Debugging
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