Sumukha Bharadwaj

About Sumukha Bharadwaj

Experience in: FPGA Design from requirement analysis till final product testing in lab environment.Skilled in: Verilog/VHDL for design and testbenches, architecture and micro-architecture design, CDC, Lint check, STA, timing closure of the design, and using ILA, VIOs to debug the design.Also- Conducted a workshop in association with World Serve at KSSEM in 2015 on \'Using MATLAB/Simulink for developing Digital Image Processing algorithms targeting an FPGA\'- One of the jury panelists for All India Paper Writing Competition on Emerging Research (PaCER 2020)- Researcher, author and presenter of two research papers in conferences.Read the papers: 1) DOI: 10.1109/IBSS.20••••••••12) DOI: 10.1109/CoCoNet.20•••••••81Achievements:Won the \"Best poster presentation\" award in an international conference, IBSS-2015, Mumbai, India.

Experience

1. Senior Fpga Design Engineer

   Capgemini Engineering

   Mar 2024 — Present · Bengaluru, IN

   FPGA design integration of DUC, DDC and RF-DC IPs into the ORAN-RU 5G design> FPGA design for CPU subsystems accessing memories through AHB interface> Involved in entire FPGA design flow - RTL design, Simulation, Synthesis, STA, Assigning Timing constraints, Timing closure, Placement and Routing, Bit stream generation and hardware debugging using ILA

Education

• SRH University

  Master of Engineering (M.Eng.), Information Technology

  2016 — 2019

• K S School of Engineering & Management (under Visvesvaraya Technological University)

  Bachelor of Engineering, Electrical, Electronics and Communications Engineering

  2011 — 2015

Skills

• Opencv
• Simulink
• C
• Vhdl
• Qt Creator
• C++
• Verilog
• Field-Programmable Gate Arrays (Fpga)
• Matlab
• Embedded Systems
• Digital Electronics
• Image Processing