Sumit Shaw
Sr. Design Verification Engineer at Cadence Design Systems
- Role
- Sr Design Verification Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sumit Shaw
Good understanding of ASIC and FPGA Verification. Extensive experience in writing RTL model using Verilog HDL. Good experience in writing Test benches using System Verilog and UVM. Expertise in Programming Language C, C++, Assembly & Perl. Hands-on Experience in Router Designing, AMBA AHB to APB Bridge Design and Verification, UART, RISC-V Processor Design and Verification. Good knowledge of Code coverage & Functional coverage and Hands-on Experience in writing linear and self-checking TB Experience in using industry-used EDA tools like Mentor Graphics Questasim, Aldec riviera-pro, Xilinx ISE for front-end design and verification.
Experience
Sr Design Verification Engineer
May 2022 — Present · Bengaluru, IN
Education
CHANDIGARH UNIVERSITY
Bachelor of Technology - BTech
2016 — 2020
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