Sumit Pandey

About Sumit Pandey

RTL Design Engineer With 9+ Years Of Experience in VLSI industry. Technical Responsibilities :Understanding of protocol specification, defining microarchitecture specifications, implementation using HDL(Verilog/System Verilog), Unit level functional verification, Synthesis (Timing sign off in high speed and high performance pipelined designs), Lint and CDC checks.Specialties : Hands on experience of industry leading protocols and technology (JEDEC DDR4,DDR5,LPDDR5, RDIMM, LRDIMM, MRDIMM, AMBA- AXI4, BLE 5.0, 5.1 and 5.2).Languages : Verilog, System VerilogTools : NCSIM(Simulator), HAL,Superlint -LINT, Jasper(CDC), Genus(Synthesis), Conformal(LEC), ETS (STA).Revision Control : GIT, SVN Scripting : TCL, Perl Strong engineering professional with a M.Tech degree (WILP) focused in Microelectronics from BITS Pilani.

Experience

1. Principal Design Engineer

   Cadence

   Jul 2023 — Present · Bengaluru, IN

Education

• D.A.V high school

  Higher Secondary, Science

  2010 — 2012

• Sodepur Colliery High School, Asansol

  Matriculation

  2005 — 2010

• Silicon Institute of Technology (SIT), Sambalpur

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2012 — 2016

• BITS Pilani Work Integrated Learning Programmes

  Master of Technology - MTech, Microelectronics