Sumit More

About Sumit More

8+ years of proven track-record & industry experience in RTL to GDSII Physical Design. Successfully taped out multiple low-power, high performance CPU blocks at leading edge tech nodes.

Experience

1. Design Engineer

   Apple

   Apr 2016 — Present · Austin, TX, US

   Working on synthesis to GDS of multiple CPU blocks. Responsible for meeting timing and power requirements and clean chip tape-out. Involved in multiple tape-outs in leading edge technology nodes- Responsible for block level place and route tasks including Synthesis, Floorplanning, budgeting, Power grid generation, Placement, Clock Tree Synthesis, Route, Timing Closure, Low Power design, Signal Integrity Analysis, and IR drop Closure- Responsible for feasibility study of the new features to be added in the block by close interaction with RTL teams. Handled complex block with multiple power domains and multiple clock domains- Worked on post Layout timing closure using Synopsys Primetime across different PVT corners and operational modes. Responsible for Low power verification, LEC, DRC-LVS checks on the block- Familiar with Gate level simulation. Helped team with debugs on regular & power aware gatesim of CPU.

Education

• Portland State University

  Master's Degree, IC Design, Test & Validation

  2014 — 2016

• COEP Technological University

  BTech, Electronics and telecommunication

  2006 — 2010

Skills

• Vhdl
• Application-Specific Integrated Circuits (Asic)
• Tcl
• Xilinx
• Circuit Design
• Functional Verification
• Design Rule Checking (Drc)
• Very-Large-Scale Integration (Vlsi)
• Computer Architecture
• Physical Design
• Integrated Circuits (Ic)
• Verilog
• Fpga
• Perl
• Asic
• Ic
• Static Timing Analysis
• Field-Programmable Gate Arrays (Fpga)
• Integrated Circuit Design
• Vlsi
• Drc