Sumit Kakade
Physical Design Floorplanning Engineer
- Role
- Physical Design Floorplanning Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sumit Kakade
I am working as Physical Design Floorplanning Engineer @intel from October, 2019.My domain experience is in below areas,Design Planning/Full chip Floorplaning/Partitioning. Pin placement, feedthrough planning, HFN handling.Macro/Global cell placementTop level Power implementation -> Bump Planning, Top Metal (RDL) routings.Hands on Physical Design (Synthesis, power, CTS, PNR)Full chip Assembly+LV execution.Scripting:Expertise with tcl scripting with tcl supported tools.Good Hands on perl/shell/python scripting.Apart from technical subjects, I believe my social skills are excellent.
Experience
Physical Design Floorplanning Engineer
Sep 2019 — Present · Bangalore, IN
Education
Vellore Institute of Technology
Master of Technology - MTech, vlsi
2017 — 2019
Pimpri Chinchwad Education Trust'S. Pimpri Chinchwad College Of Engineering
Bachelor of Engineering - BE, Electrical, Electronic and Communications Engineering Technology/Technician
2011 — 2015
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