Sumeet Rathore

About Sumeet Rathore

Currently contributing to Synopsys Inc. as an ASIC Design Verification Engineer, focusing on the verification and enhancement of M-PHY IP testbenches. Played a key role in developing and verifying the H8ULP feature, achieving full code and functional coverage closure through structured verification plans. Collaborated with design teams to execute gate-level simulations, resolve timing violations, and attain functional and timing closure. Graduated with a B.Tech in Electronics from Birla Vishvakarma Mahavidyalaya and in Electrical and Electronics Engineering from Gujarat Technological University. Proficient in RTL and functional verification, with hands-on experience in SystemVerilog, UVM, and Verilog. Dedicated to advancing semiconductor solutions through methodical verification techniques and team collaboration.

Experience

1. Asic Design Verification Engineer

   Synopsys Inc

   Jul 2023 — Present

   Focused on verification and enhancements of Synopsys M-PHY IP (V5) testbench.•Successfully developed and verified the H8ULP feature using a structured verification plan, achieving completion of all targeted metrics, including test cases, scenarios, and 100% code and functional coverage closure.•Executed gate-level simulation (GLS) for the M-PHY IP testbench, reporting design issues and resolving timing violations to achieve functional and timing closure.•Created and executed power state table(UPF) coverage plans using structured vPlans, achieving 100% power state table coverage closure.•Collaborated with design teams to analyze the M-PHY V6 specification and architecture, and developed detailed verification and coverage plans, ensuring complete feature validation and coverage closure.•Played a key role in enhancing and extending the M-PHY V5 UVM testbench for M-PHY V6 migration, incorporating new features such as datapath, test mode, EyeMon, H8ULP, and adaptation.•Developed functional coverage models, protocol-level assertions, and new testcases for M-PHY V6, ensuring thorough feature validation and verification completeness.

Education

• Birla Vishvakarma Mahavidyalaya

  Bachelor of Technology - BTech, Electronics

  2017 — 2021

• Gujarat Technological University

  Bachelor of Technology, Electrical and Electronics Engineering