Sumeet Pawar
Design Verification Engineer at Apple
- Role
- Design Verification Engineer at Apple
- Location
- Mountain View, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Sumeet Pawar
HDL/HVL: UVM/OVM, SystemVerilog, Verilog. Programming Languages: C, C++, Python, OOP. Architecture: MIPS Architecture/Assembly.Tools: Synopsys VCS, Questa Sim, Synopsys DC.Operating Systems: Linux/Unix.
Experience
Design Verification Engineer
Jul 2021 — Present · Cupertino, CA, US
Education
Pillai College of Engineering
BE - Bachelor of Engineering, Electronics and Telecommunication engineering
2014 — 2018
Portland State University
Master's degree, Electrical and Computer Engineering
2019 — 2021
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