Sumeet Gulati

Senior Principal Engineer @NXP Semiconductors

San Jose, CA, US
EMAILS
s••••••••@nxp.com
MOBILE NUMBERS
+91 *********19

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WORK HISTORY

Jul 2022 — Present

Senior Principal Engineer @NXP Semiconductors

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San Jose, CA, US

EDUCATION

2000 — 2004

Dehradun Institute of Technology( DIT )

B.Tech, Electronics & Communications

2004 — 2006

Indian Institute of Technology, Guwahati

Master of Technology (M.Tech.), Digital Signal Processing

ABOUT SUMEET GULATI

Master\'s Degree in Digital Signal Processing DSP from IIT Guwahati, with 19 years of experience in pre-silicon functional verification and post-silicon validation activities of Digital and Mixed signals ASICs/SoCs in IP, Subsystem, Full Chip, and Multi-Chip scenarios.Verification sign-off of more than 15 Products, besides multiple others First Time Right functional Silicons.This led to 2.5 billion+ units of ASICs/SoCs product sales with less than 10 PPM field returns.Incubated range of products from DSP-based Smart Class D Smart Amplifier, Haptic Drivers, Temperature sensors, PMICs, Digital Car Radios, Audio SoCs, RTCs, LCD/LED/Graphics Drivers, DigitalTV SoCs, GPON Network ASICs/FPGAs.Experience in leading responsible roles as Verification Engineer, Digital Lead, IP architect, Verification Lead and Verification Architect. Lead teams of sizes from small two to as large as ten members.My main responsibilities in my current role are + Verification Architect, building & integrating UVM environments for IP, Subsystems, Full Chip to Multi-Chip level, from scratch.+ Verification Planning and Strategies for methodologies,flows, effort estimation, allocations, progress tracking.+ Class-Based System Verilog SV implementation of UVCs, UVM environments, with or without third-party UVCs.+ Low Power Simulation of multi-power domain ASICs/SoCs.+ Performance verification and post-simulation data/signal analysis in Matlab, and C/C++ models+ Regressions management for a variety of runs Digital-Analog Mixed Simulations and firmware co-simulations.+ Traceable Verification specifications of test items, coverage items, checkers/models/assertions.+ Verification sign-off on functional, code, test coverages, and timing GLS.+ Post Silicon Validation: 5 Days Silicon Bring-ups, industrial tests to functional validation and electrical characterization.

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