Sumanth Krishna Kilaru
physical design engineer II at Intel Corporation| m.tech vlsi design nit jalandhar 21\'
- Role
- Sta Engineer at Intel
- Location
- Jalandhar, PB, IN
- LinkedIn followers
- 500 followers
About Sumanth Krishna Kilaru
2+ years of industry experience• 1+-years’ experience as STA engineer and 1 year as a physical design intern• MTech in VLSI design from NIT Jalandhar with a CGPA of 8.09• Experience in analyzing timing reports and closing timing for 5nm and 3nm complex CPU blocks• Expertise in 7nm technology nodes at soc level block-level implementations from RTL2GDSII and Netlist2GDSII• Dealing with blocks whose cell count is >2M at higher frequencies• Knowledge of Signoff Checks (DRC, LVS, FEV, Timing Analysis, Antenna Checks) • Expertise in Power/IR Drop/EM analysis• Developed several automation codes in TCL to optimize manual tasksK sumanth k••••••••@gmail.com
Experience
Sta Engineer
Jul 2020 — Present · Bengaluru, IN
physical design implementation at block level in 7nm technology. responsible for logical synthesis physical synthesis,APR, timing closure, power closure, signoff checks closure
Education
Velagapudi Ramakrishna Siddhartha Engineering College
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2014 — 2018
NIT Jalandhar
Master of Technology - MTech, VLSI design
2019 — 2021
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