Sumanth Batchu

About Sumanth Batchu

Logic Design Engineer with 7 years of Industrial experience in Digital Design, Verification and Timing Closure. Created FPGA emulation models from SOC RTL using Synopsys protocompiler tool targeting for HAPS 80.• Replaced Legacy Asynchronous Resource Bus interface with AXI for on chip communication • Modified all the Legacy IP to add AXI slave interface• Designed SPI Master and Slave IP • Designed 24-bit LCD Display IP which can be used as TBE for LCD display • Upgraded DDR3 Controller IP and USBFX3 IP to increase the Data Throughput • Helped team to Develop a Modular Next Gen validation Platform for pre-silicon and post Silicon Validation• Created FPGA emulation models from RTL using Synopsys protocompiler tool • Partitioned Big Designs across 8 Ultra scale FPGA using 2 HAPS 80 platforms• Develop Hardware Collateral to be integrated with the FPGA emulation model• Test and Debug the FPGA emulation models• Develop and maintain model build flows, debug capabilities• Familiar with ARM cortex M7 processor• Worked with Xilinx PCIE PHY in UltraScale and UltraScale+• Worked Closely with Design teams and software teams across multiple sites

Experience

1. Asic Engineer

   Meta

   Dec 2022 — Present · Austin, TX, US

Education

• Arizona State University

  Master of Science (MS), Electrical Engineering

  2013 — 2015

• JNTU Kakinada

  Bachelor of Technology (BTech), Electronics and Communication Engineering

  2009 — 2013

Skills

• Fpga
• Asic
• Electronics
• Microcontrollers
• Mips
• Linux
• Modelsim
• Rtl Design
• Cadence Virtuoso
• Testing
• Electrical Engineering
• Powerpoint
• Microsoft Excel
• Semiconductors
• Multisim
• Cadence Spectre
• Perl
• Xilinx
• Systemverilog
• Logic Design
• C
• Programming
• Verilog
• Pspice
• Vhdl
• Matlab
• Soc
• Digital Electronics
• Simulink
• Keil
• Microsoft Office
• Vlsi
• Debugging
• C++
• Circuit Design
• Labview